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山东大学学报 (工学版) ›› 2026, Vol. 56 ›› Issue (2): 43-51.doi: 10.6040/j.issn.1672-3961.0.2025.057

• 机器学习与数据挖掘 • 上一篇    

基于LSTM的逻辑综合阶段延时预测方法

王庆康1,周冉冉1*,王永1,2   

  1. 1.山东大学集成电路学院, 山东 济南 250101;2.泉城实验室, 山东 济南 250103
  • 发布日期:2026-04-13
  • 作者简介:王庆康(1999— ),男,安徽滁州人,硕士研究生,主要研究方向为电子设计自动化. E-mail:qingkangw@mail.sdu.edu.cn. *通信作者简介:周冉冉(1990— ),女,山东泰安人,高级实验师,硕士生导师,博士,主要研究方向为集成电路设计与自动化. E-mail:rzhou@sdu.edu.cn
  • 基金资助:
    国家重点研发计划资助项目(2021YFA1003604);国家自然科学基金资助项目(U23A20348)

A logic synthesis delay predicting method based on LSTM

WANG Qingkang1, ZHOU Ranran1*, WANG Yong1,2   

  1. WANG Qingkang1, ZHOU Ranran1*, WANG Yong1, 2(1. School of Integrated Circuits, Shandong University, Jinan 250101, Shandong, China;
    2. Quan Cheng Laboratory, Jinan 250103, Shandong, China
  • Published:2026-04-13

摘要: 为了提高数字集成电路逻辑综合阶段的延时评估精度与效率,提出一种基于长短期记忆网络(long short-term memory,LSTM)的逻辑综合阶段延时预测方法。将时序路径表示为由标准单元构成的有序序列,提取并构建包含单元类型、扇出、负载电容和输入转换时间等关键特征参数的结构化序列数据;通过LSTM时序建模中的上下文记忆能力,捕捉路径中各级单元之间复杂的时序依赖关系,实现对路径延时的高精度预测。试验结果表明,对比现有对单元延时和线延时进行累加的机器学习估算方法,在预测精度上,基于LSTM的预测方法在保证高准确率的前提下,对不同类型的案例具有更好的适应性;在运行速度上,在多数测试案例上实现2.8~3.2倍加速。在无工艺信息的通用门级网表上验证本研究方法的预测能力,其表现优于传统静态时序分析方法,验证了该方法在早期设计阶段的有效性和应用前景。

关键词: 长短期记忆网络, 逻辑综合, 静态时序分析, 路径延时预测, 机器学习

Abstract: To improve the prediction accuracy and efficiency for logic synthesis in digital integrated circuit design process, a logic synthesis delay predicting method based on long short-term memory(LSTM)was proposed. The timing path was treated as an ordered sequence of standard cells, and key feature parameters such as cell type, fanout, load capacitance, and input transition time were extracted and organized into structured sequence data. With the context memory capability of LSTM-based timing modeling, the complex timing dependencies between cells at different levels in the path were captured, achieving high-precision prediction of path delay. Experimental results showed that, compared to existing machine learning-based estimation methods that accumulate cell delays and wire delays, the LSTM-based prediction method demonstrated better adaptability to different types of cases while maintaining accuracy. In terms of running speed, a speedup of 2.8 to 3.2 times was achieved in most test cases. The prediction method was also validated on generic netlists without technology information and the performance was superior to traditional static timing analysis methods, demonstrating its effectiveness and potential for early-stage design applications.

Key words: long short-term memory, logic synthesis, static timing analysis, path delay predicting, machine learning

中图分类号: 

  • TP319
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