山东大学学报 (工学版) ›› 2026, Vol. 56 ›› Issue (2): 43-51.doi: 10.6040/j.issn.1672-3961.0.2025.057
• 机器学习与数据挖掘 • 上一篇
王庆康1,周冉冉1*,王永1,2
WANG Qingkang1, ZHOU Ranran1*, WANG Yong1,2
摘要: 为了提高数字集成电路逻辑综合阶段的延时评估精度与效率,提出一种基于长短期记忆网络(long short-term memory,LSTM)的逻辑综合阶段延时预测方法。将时序路径表示为由标准单元构成的有序序列,提取并构建包含单元类型、扇出、负载电容和输入转换时间等关键特征参数的结构化序列数据;通过LSTM时序建模中的上下文记忆能力,捕捉路径中各级单元之间复杂的时序依赖关系,实现对路径延时的高精度预测。试验结果表明,对比现有对单元延时和线延时进行累加的机器学习估算方法,在预测精度上,基于LSTM的预测方法在保证高准确率的前提下,对不同类型的案例具有更好的适应性;在运行速度上,在多数测试案例上实现2.8~3.2倍加速。在无工艺信息的通用门级网表上验证本研究方法的预测能力,其表现优于传统静态时序分析方法,验证了该方法在早期设计阶段的有效性和应用前景。
中图分类号:
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