关键词: 多项式插值, Verilog, 后台校正, 插值算法, 流水线ADC

Abstract: In the background calibration, the residual amplifier transfer function modeling was applied to estimate the errors for improving the performance of pipeline analog to digital converter (ADC). To find a compromise among calibration resolution, hardware consumption, power consumption and the convergence time, an interpolation algorithm was needed to be chosen. Using a 12 bits 40 M sample rate pipeline ADC as prototype, the piecewise linear and cubic polynomial were respectively used to model the first stage inter-stage amplifier transfer function. The model was described by verilog, and the analog-digital mixed simulation was put forth by the analog circuit. The code was synthesized to estimate the overhead of the two algorithms. Simulation results showed that piecewise linear interpolation consumered less hardware and power consumption between these two algorithms, while the cubic polynomial interpolation was more precise and convergences faster.

Key words: pipeline ADC, interpolation algorithm, polynomial interpolation, Verilog, background calibration