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山东大学学报(工学版) ›› 2013, Vol. 43 ›› Issue (3): 99-104.

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基于BiCMOS的高性能CML三值D型触发器的设计

赵祥红1,2,沈继忠2*   

  1. 1. 浙江大学宁波理工学院信息科学与工程学院, 浙江 宁波 315100; 
    2. 浙江大学信息与电子工程学系, 浙江 杭州 310027
  • 收稿日期:2012-12-05 出版日期:2013-06-20 发布日期:2012-12-05
  • 通讯作者: 沈继忠(1965- ),男,浙江宁波人,教授,博士研究生导师,主要研究方向为低功耗设计,数字集成电路与系统设计,BCI等. E-mail:jzshen@zju.edu.cn
  • 作者简介:赵祥红(1981- ),男,湖北天门人,硕士研究生,主要研究方向为数字系统设计和低功耗设计的研究. E-mail: zxh@nit.net.cn
  • 基金资助:

    国家自然科学基金资助项目(61071062); 宁波市自然科学基金资助项目(2011A610109)

Design of highperformance CML ternary D flipflop based on BiCMOS

ZHAO Xiang-hong1, 2, SHEN Ji-zhong2*   

  1. 1. Ningbo Institute of Technology, Zhejiang University, Ningbo 315100, China;
    2. Department of Information Science & Electronic Engineering, Zhejiang University, Hangzhou 310027, China
  • Received:2012-12-05 Online:2013-06-20 Published:2012-12-05

摘要:

结合电流模逻辑(currentmode logic, CML)电路的高速低摆幅、抗干扰能力强、适合在高频下工作的优点以及BiCMOS电路高速大驱动的优点,设计了一种结构简单的基于BiCMOS的高性能CML三值D型触发器。采用TSMC 180nm工艺,使用HSPICE进行模拟。结果表明,所设计的触发器不仅具有正确的逻辑功能,且结构简单,与目前先进的三值D型触发器相比,平均D-Q延时降低95.6%~98.4%,PDP降低16.2%~96.8%,同时工作频率可高达15GHz,适合高速和高工作频率的应用。

关键词: 触发器, 多值逻辑, 电流模逻辑, 低功耗, 高速集成电路

Abstract:

A simple-structure high-performance CML ternary D flip-flop based on BiCMOS was proposed, which combined both advantages of BiCMOS and CML circuits, and included high-speed and strong drive ability of BiCMOS circuits and high speed low swing and low noise of CML circuits. Using TSMC 180nm process, the results of simulations carried out by HSPICE illustrated that the proposed circuit could not only have correct logic function, but also gain improvements of 95.6%-98.4% in average D-Q delay and 16.2%-96.8% in PDP compared with the advanced ternary D flip-flops. Furthermore, the work frequency  could perform up to 15GHz. All of the results proved that the proposed circuit was suitable for high-speed and high-frequency applications.

Key words:  flip-flop, multi-valued logic, current-mode logic, CML, low-power, high-speed integrated circuits

中图分类号: 

  • TN43
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