Journal of Shandong University(Engineering Science) ›› 2026, Vol. 56 ›› Issue (2): 43-51.doi: 10.6040/j.issn.1672-3961.0.2025.057

• Machine Learning & Data Mining • Previous Articles    

A logic synthesis delay predicting method based on LSTM

WANG Qingkang1, ZHOU Ranran1*, WANG Yong1,2   

  1. WANG Qingkang1, ZHOU Ranran1*, WANG Yong1, 2(1. School of Integrated Circuits, Shandong University, Jinan 250101, Shandong, China;
    2. Quan Cheng Laboratory, Jinan 250103, Shandong, China
  • Published:2026-04-13

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Abstract: To improve the prediction accuracy and efficiency for logic synthesis in digital integrated circuit design process, a logic synthesis delay predicting method based on long short-term memory(LSTM)was proposed. The timing path was treated as an ordered sequence of standard cells, and key feature parameters such as cell type, fanout, load capacitance, and input transition time were extracted and organized into structured sequence data. With the context memory capability of LSTM-based timing modeling, the complex timing dependencies between cells at different levels in the path were captured, achieving high-precision prediction of path delay. Experimental results showed that, compared to existing machine learning-based estimation methods that accumulate cell delays and wire delays, the LSTM-based prediction method demonstrated better adaptability to different types of cases while maintaining accuracy. In terms of running speed, a speedup of 2.8 to 3.2 times was achieved in most test cases. The prediction method was also validated on generic netlists without technology information and the performance was superior to traditional static timing analysis methods, demonstrating its effectiveness and potential for early-stage design applications.

Key words: long short-term memory, logic synthesis, static timing analysis, path delay predicting, machine learning

CLC Number: 

  • TP319
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